GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Hanrui Wang 1 , Kuan Wang 1 , Jiacheng Yang 1 , Linxiao Shen 2 , Nan Sun 2 , Hae-Seung Lee 1 , Song Han 1
1Massachusetts Institute of Technology, 2University of Texas at Austin

Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance trade-offs, and fast technological advancements. Although there has been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black-box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search, and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

Graph Neural Networks as RL Agent

The circuit topology is embedded as a graph in which edges are circuit wires and vertices are circuit components (transistors, capacitors, etc.).

FoM Comparisons on Four Circuits

GCN-RL achieves the highest FoM values on different benchmarks.

Knowledge Transfer between Technology Nodes

GCN-RL enables knowledge transfer between technology nodes, thus reducing re-design overhead.


    title     = {GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning},
    author    = {Wang, Hanrui and Wang, Kuan and Yang, Jiacheng and Shen, Linxiao and Sun, Nan and Lee, Hae-Seung and Han, Song},
    booktitle = {The 57th Design Automation Conference (DAC)},
    year      = {2020}

Acknowledgments: We sincerely thank NSF Career Award #1943349, MIT Center for Integrated Circuits and Systems, Samsung, MediaTek for supporting this research. We also thank Dr. John Cohn for valuable discussion.